The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices. It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s or 12.5 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards.

• Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector
• >0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, SSC and residual SSC
• Excellent signal performance and sensitivity
• Built-in clock data recovery with tunable and compliant loop bandwidth
• Half-rate clocking with variable duty cycle for forwarded clocked devices
• Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture
• PRBS and pattern with 60 block pattern sequencer
• All options are retrofittable and upgrade from N4903A possible
• New for N4903B:
  • Always comes with built-in tunable and compliant CDR
  • True differential inputs to match today’s ports
  • Built-in CDR for clockless data
  • Auto-alignment of sampling point
  • Bit recovery mode for unknown data traffic (Option AO1)
  • Burst mode for testing recirculation loop
  • BER result and measurement suite
  • Quick eye diagram and mask with BER contours