The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices. It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s or 12.5 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards.
002 | Pattern and Pseudo Random Pattern Sequence (PRBS) on Auxillary Data Output License |
003 | Half-rate clocking and Duty Cycle Distortion |
A-01 | Bit Recovery Mode |
A-02 | Symbol Error Ratio and Frame Error Ratio (SER/FER) Analysis |
D14 | Extended Pattern Generator Data Rate to 14.2 Gb/s |
G07 | Pattern Generator 150 Mb/s to 7 Gb/s |
G13 | Pattern Generator 150 Mb/s to 12.5 Gb/s |
J10 | Jitter Injection |
J11 | Spread Spectrum Clocking |
J12 | Jitter Compliance Suite |
J20 | Interference Channel (ISI and Sinusoidal Interference) |
Form Factor |
---|
Plug-In |