Tektronix BSA286CL

BERTScope 28.6 Gb/s Bit Error Rate Analyzer
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Description

The BERTScope Bit Error Rate Tester Series provides a new approach to signal integrity measurements of serial data systems. Perform bit error rate detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope Bit Error Rate Tester Series enable you to easily isolate problematic bit and pattern sequences, then analyze further with advanced error analysis that deliver unprecedented statistical measurement depth.

Key performance specifications

  • Pattern Generation and Error Analysis, High-speed BER Measurements up to 28.6 Gb/s
  • Fast Input Rise Time / High Input Bandwidth Error Detector for Accurate Signal Integrity Analysis
  • Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates
  • Integrated Eye Diagram Analysis with BER Correlation
  • Optional Jitter Map Comprehensive Jitter Decomposition - with Long Pattern (i.e. PRBS-31) Jitter
  • Patented Error Location Analysis™ enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis

Key features

  • Integrated, calibrated stress generation to address the stressed receiver sensitivity and clock recovery jitter tolerance test requirements for a wide range of standards
    • Sinusoidal jitter to 100 MHz
    • Random jitter
    • Bounded, uncorrelated jitter
    • Sinusoidal interference
    • Spread spectrum clocking
    • PCIe 2.0 & 3.0 receiver testing
    • F/2 jitter generation for 8xFC and 10GBASE-KR testing
    • IEEE802.3ba & 32G fibre channel testing
  • Electrical stressed eye testing for
    • PCI express
    • 10/40/100 Gb Ethernet
    • SFP+/SFI
    • OIF/CEI
    • Fibre channel (FC8, FC16, FC32)
    • SATA
    • USB 3.1 
    • InfiniBand (SDR, QDR, FDR, EDR)
  • Tolerance compliance template testing with margin testing
  • Integrated eye diagram analysis with BER correlation

Applications

  • Design verification including signal integrity, jitter, and timing analysis
  • Design characterization for high-speed, sophisticated designs
  • Certification testing of serial data streams and high performance Networking systems
  • Design/Verification of high-speed I/O components and systems
  • Signal integrity analysis – mask testing, jitter peak, BER contour, jitter map, and q-factor analysis
  • Design/Verification of optical transceivers
List of Options
4T 4-Tap Digital Pre-emphasis Processor
C3 Calibration Service 3 Years
CA1 Provides a single calibration event or coverage
ECC Add Error Correction Coding Emulation SW (included in STR)
ECM Eye Opener, Clock Multiplier, Clock Doubler
F2 F/2 Jitter Generation at 8G/10.3125G (requires STR)
J-MAP Add Jitter Decomposition SW
JTOL Add Jitter Tolerance Templates SW (included in STR)
LDA Add Live Data Analysis SW
MAP Add Error Mapping Analysis SW (included in STR)
PCISTR Add PCIe Gen2 Extended Stress Generation
PL Add Physical Layer Test Suite SW (included in STR)
PVU Add PatternVu Equalization Processing SW
R3 Repair Service 3 Years (including warranty)
R3DW Repair Service Coverage 3 Years (includes product warranty period). 3-year period starts at time of customer instrument purchase
SF Add Symbol Filtering option SW (used with STR) 1
SLD Add Stressed Live Data option SW
STR Stressed Signal Generation (includes option ECC, MAP, PL, XSSC, JTOL)
XSSC Extended Spread Spectrum Clocking (SSC) (included in STR)

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