The BERTScope Bit Error Rate Tester Series provides a new approach to signal integrity measurements of serial data systems. Perform bit error rate detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope Bit Error Rate Tester Series enable you to easily isolate problematic bit and pattern sequences, then analyze further with advanced error analysis that deliver unprecedented statistical measurement depth.
Key performance specifications
Key features
Applications
4T | 4-Tap Digital Pre-emphasis Processor |
C3 | Calibration Service 3 Years |
CA1 | Provides a single calibration event or coverage |
ECC | Add Error Correction Coding Emulation SW (included in STR) |
ECM | Eye Opener, Clock Multiplier, Clock Doubler |
F2 | F/2 Jitter Generation at 8G/10.3125G (requires STR) |
J-MAP | Add Jitter Decomposition SW |
JTOL | Add Jitter Tolerance Templates SW (included in STR) |
LDA | Add Live Data Analysis SW |
MAP | Add Error Mapping Analysis SW (included in STR) |
PCISTR | Add PCIe Gen2 Extended Stress Generation |
PL | Add Physical Layer Test Suite SW (included in STR) |
PVU | Add PatternVu Equalization Processing SW |
R3 | Repair Service 3 Years (including warranty) |
R3DW | Repair Service Coverage 3 Years (includes product warranty period). 3-year period starts at time of customer instrument purchase |
SF | Add Symbol Filtering option SW (used with STR) 1 |
SLD | Add Stressed Live Data option SW |
STR | Stressed Signal Generation (includes option ECC, MAP, PL, XSSC, JTOL) |
XSSC | Extended Spread Spectrum Clocking (SSC) (included in STR) |