PCI Express 2.0 introduces new
challenges for validation engineers.
Time to market pressures require a
solution that can quickly pinpoint
problems. The TLA7Sxx Series serial
analyzer modules provide an innovative
approach to PCI Express validation that
spans all layers of the protocol from the
physical layer to the transaction layer.

For the first time, parallel and serial
acquisition modules can be utilized in
both the TLA7012 portable mainframe
and the TLA7016 benchtop mainframe
offering the highest degree of flexibility.
Additionally, the TLA7Sxx Series serial
analyzer modules have unsurpassed
ability to capture and trigger on PHY
layer events, whether problems exists
during link training or while the link is
going into or out of power management
states. Complete support for L0s and
L1 power management is critical as
power saving techniques become more
prevalent in system designs. The
TLA7Sxx Series serial analyzer
acquisition capability is complemented
by analysis tools which provide protocol
decode and error reporting capabilities.

Hardware developers, hardware/software
integrators and embedded
system designers will appreciate the
tight integration with the Tektronix Logic
Analyzer. Correlation with other system
buses or general purpose debug
signals uses the TLA common system
timestamp. Elusive problems that may
have been propagated from other
system buses can be efficiently
debugged in a single environment.

Coupled with the P67xx Series mid-bus
probes engineers have flexible options
for platform accessibility.

Features:

• 8/16 Channel Serial Analyzer Modules with 32M 8b/10b Symbols Memory Depth per Channel
• 2.5 Gb/s and 5 Gb/s Acquisition Speed for PCI Express 1.0 and PCI Express 2.0
• Frequency Margining at 2.5 Gb/s +/- 10% or 5.0 Gb/s +/- 10%
• Supports x1, x2, x4, x8, and x16 PCI Express Links
• Sync to L0s within 12 FTS Packets (typical)
• Track 2.5 Gb/s to 5.0 Gb/s Data Rate Change
• Dynamically Track Changes in Link Width
• Powerful Trigger State Machine Spans all Layers of the Protocol (Physical, Data Link, and Transaction)
• Hardware Filtering Extends Link Capture Time
• Compression Probing System Provides Minimal Intrusion on Circuits
• Internal or External Reference Clock with or without Spread Spectrum Clocking (SSC)
• Protocol Decode and Error Reporting in Listing and Waveform Views
• Real Time Link Status Indicators