TSG422 Features Conforms to ITU-R BT. 601/656, EBU Tech 3267, and SMPTE 125M, 259M, and RP165 10- or 8-Bit Signal Generation Parallel Digital Video Test Signal Outputs Four Serial Digital Video Outputs (Opt. 1S) Separate Y, B-Y, R-Y Clock Outputs 525/60 and 625/50 Operation NTSC or PAL Black Burst Outputs Sync Lock to 525/60 or 625/50 Applications D1 VTR and Other 4:2:2 Component Digital Equipment Testing and Maintenance The TSG422 Digital Component Generator is a CCIR 601, 4:2:2 format digital test signal generator. The TSG422 provides all the test signals needed to operate, maintain and evaluate 4:2:2 digital equipment. Analog black burst outputs are provided for equipment synchronization. Test Signal Generator The TSG422 signal generation is 10-Bit in all channels and is clocked at 13.5 MHz for the luminance channel and 6.75 MHz for the color difference channels. Color difference samples are co-sited with the odd numbered luminance samples. The TSG422 signal complement contains general purpose signals plus those tailored specifically to the 4:2:2 environment. Test signals included are: SMPTE color bars Color bars (100% and 75%) Pluge 5-step Ramp Limit ramp Valid ramp Modulated ramp Light blue shallow ramp Shallow ramp Shallow ramp matrix Pulse and bar Field square wave Co-siting verification Multipulse Multiburst Full and reduced amplitude sweeps Bowtie timing 50% flat field Convergence pattern Digital/analog blanking markers Digital gray Super black APL: high, low and bounce The ramp signal extends 5% below blanking and 5% above peak white to provide indication of clipping. The limit ramp provides signal information to test the maximum dynamic range of the system, levels 4 through 1016 in a 10-Bit system. Shallow ramp, shallow ramp matrix and light blue shallow ramp are provided for measurement of quantization noise and the detection of rounding and truncation errors. The co-siting signal provides a one sample wide, peak white pulse on each horizontal scan line. The luminance channel pulse occurs on an odd sample and is coincident with the like pulses in the color difference channels. This signal is intended to provide an easy means of verifying correct luminance and color difference sample positioning in both the digital and analog domains. The TSG422 now provides a new signal for determining the blanking to active picture relationship in a digital television signal, as well as the relative timing between two different digital signals. This signal, the Active Picture Timing Test Signal, provides markers for both digital and analog, vertical and horizontal blanking location. The digital gray signal sets the luminance channel to word 508 and the color difference channel to word 512. This sets up a high/low sequence on each of the parallel interface lines, thus providing a high frequency signal for testing of the transmission medium. The TSG422 also provides facilities for time offsetting the clock and data information. This is useful in verifying receiver performance. In addition, the frequency of the 27 MHz interface clock may be shifted by 200 Hz in either direction. This provides a means for testing phase lock loops in clock regeneration circuits. Two separate digital test signal outputs are provided. Separate outputs of each clock signal are also provided. These outputs are useful in demultiplexing the digital test signal data for conversion to analog for further analysis. Serial Digital Video Interface The serial digital video option for the TSG422 provides four serial outputs. These are user configurable for either black or test signal. If configured for test signal, these outputs follow the front panel test signal selection. Signal specifications meet all related digital video and audio standards. An error detection (EDH) signal is located in the ancillary data area of line 9 (525 systems) or line 5 (625 systems). This signal contains two cyclic redundancy code (CRC) calculations, one for the digital data in each field and one for the digital data in the active picture of each field. Comparison of the CRC values with those calculated in the receiver will provide a real time, on-line error rate measurement. Three special flat field (SDI check field) signals are provided for serial digital interface testing. These valid component digital signals are designed to test receiver serial equalization and clock recovery. Four channels of AES/EBU digital audio are embedded in the serial digital video. Internal DIP switch selection of Frequency, Silence or Off is provided for each channel pair. In addition, the status bit may be set to indicate emphasis on or off for checking of devices with automatic detection and switching of audio de-emphasis. This feature provides functionality checking only as there is no pre-emphasis of the embedded audio at any time. Serial digital video output is available as an option for new generators and as a field upgrade kit for existing TSG422 generators. The TSG422 now provides a new signal for determining the blanking to active picture relationship in a digital television signal as well as the relative timing between two different digital signals. This signal, the Active Picture Timing Test Signal, provides markers for both digital and analog, vertical and horizontal blanking location.